1. Field of the Invention
The present invention relates to a configuration of a semiconductor memory device having a burn in test function.
2. Description of the Background Art
As dynamic random access memory (DRAM) and the like have higher degrees of integration and larger capacitance, it is important to test semiconductor memory devices to ensure their reliability before they are shipped as finished products.
In particular, there exists a chip which has electrical characteristics initially allowing it to be a good product but also has various latent defects for example of a gate insulation film and an interconnection that have been introduced during the process for fabricating the chip. It can be said that such a chip internally has a so-called “initial defect” causing the chip to fail in a relatively short period of time after an operation starts.
To enhance a product in reliability, before the product is shipped it is tested by applying stress to it to manifest such a latent defect and thus screen out the defective chip. DRAM and other similar semiconductor memory devices are thus screened not only by applying temperature stress to a chip in an environment of a high temperature but also applying electrical stress to a circuit internal to the chip to “burn-in-test” it.
Conventionally in such a burn in test if stress voltage is applied in a memory cell array between bit lines, data of a memory cell is amplified by a sense amplifier to apply voltage.
The application of stress to a bit line that depends on data previously written to a memory cell, however, is disadvantageous, as described below:
i) voltage allowed to be applied as stress between bit lines would be that which can be read from a memory cell and also amplified by a sense amplifier. For example if it is desired to apply high voltage to apply large stress to further accelerate stress between bit lines, the high voltage applied would affect a memory cell transistor, a memory cell capacitor and the like and thus get in the way of maintaining the reliability of the memory cell. As such for example it is difficult to apply large stress voltage to accelerate the test in order to maintain the reliability of a memory cell transistor, a memory cell capacitor and the like; and
ii) for a particular pattern of data that a tester apparatus can write to a memory to be tested, a particular configuration of I/O to be tested, and the like, stress voltage can hardly be applied to a bit line.
Thus the stress application is insufficient to manifest a defect existing between bit lines and as a result an chips having a latent initial defect can hardly be detected in a test of a short period of time.
Furthermore, an I/O line communicating data with the bit line also cannot receive sufficient stress if the application of stress to the bit line depends on data previously written to a memory cell.